This invention relates generally to programmable read only memory (PROM) cell structures and processes of making them, particularly erasable (EPROM), electrically erasable (EEPROM), and flash EEPROM devices.
A main component of one of these types of PROM cell structures is a floating gate whose potential controls the conduction along at least a portion of a field effect transistor ("FET") channel between its source and drain regions in a semiconductor substrate. The floating gate is surrounded by an electrically insulated dielectric. A control or select gate is capacitively coupled with the floating gate through a dielectric layer and acts as a word line to enable reading or writing of a single selected cell in a two-dimensional array of cells. A selected cell is programmed by holding the control gate and its source and drain at appropriate voltages so that an electron travels from the substrate and to the floating gate through an intervening gate oxide layer by a mechanism that is referred to as "hot channel injection". If enough electrons are so injected into the floating gate, the conductivity of the channel of the field effect transistor of which the floating gate is a part is changed. By measuring the conductivity of a selected memory cell device, therefore, it is determined whether a binary "1" or "0" is being stored. Since the floating gate is well insulated, this type of memory device is not volatile; that is, the floating gate retains its charge for an indefinite period without any power being applied to the device.
Most PROMs are made to be erasable so that the state of the individual memory cells can be reprogrammed. The earliest erasable version of such cells is an EPROM which could be erased by exposure to strong ultraviolet light for 15 or 20 minutes. After erasure, the memory cell array can be electrically reprogrammed. More recently, EEPROM devices have been provided that allow the electrical erasure of individual addressed memory cells or designated groups of memory cells. During such erasure, the control gate, source and drain are held at a potential that causes the electrons to tunnel back through the gate oxide to the substrate region, usually the source. This can reverse the effect of an earlier programming by hot channel injection of electrons to the floating gate. Electrically erasable memory arrays which allow a large block of memory cells, or the entire array, to be erased at the same time, are known as "flash" EEPROMs. (That is, the entire memory array, or a large portion of it, is erased in a "flash".)
A specific form of a flash EEPROM structure utilizes a separate erase gate in addition to the control gates. The erase gate is capacitively coupled to the floating gate through a tunnel dielectric which allows electrons to travel through it from the floating gate to the erase gate upon the correct combination of voltages being applied to the control gate, erase gate, source and drain. The gates are generally formed by depositing polycrystalline silicon, which is then doped ("polysilicon"). The three gates are generally constructed from separate polysilicon layers (triple-poly) that are deposited and etched in sequence, along with deposition or growth of an insulating dielectric, usually oxide, between them. Asperities are usually formed on a surface area of the floating gate. The asperities, or roughness, on the surface of the floating gate help to concentrate electric fields to assist emission of electrons from the floating gate, which then travel through the tunnel dielectric and onto the erase gate.
It is currently a goal of many in the development of these types of non-volatile memory devices to provide an array having millions of individual memory cells on a single silicon integrated circuit chip of practical size. Sixteen and 64 megabit memory cells are currently contemplated. This trend requires that the silicon substrate area occupied by each cell be reduced as the number of cells placed on a single chip increases. This scaling down of the cell array structure has encountered several limitations.
One such limitation is the necessity for the capacitive coupling between the floating gate and the control gate to be maintained high in all of the PROM, EPROM and EEPROM devices. Specifically, in the case of a triple-poly flash EEPROM device, that capacitance should be equal to or greater than 70 percent of the total capacitive coupling of the floating gate with that and all other elements of the memory cell. That total capacitance includes coupling with the control gate, mentioned previously, plus coupling with the substrate and erase gate. Reducing the size of typical flash EEPROM cells does not reduce each of these capacitances proportionately, but rather reduces the floating gate/control gate capacitance in much greater proportion. Therefore, in order to maintain the high level of capacitive coupling between the floating gate and control gate, in light of the coupling area being reduced when the cell is made smaller, others have drastically reduced the thickness of the dielectric layer between them. The thin dielectric, usually an oxide layer grown on the floating gate polysilicon, however, has a higher failure rate and is difficult to maintain a high manufacturing yield. These factors limit the amount of adjustment in capacitance that can be provided by the thinner oxide to overcome the effect of the smaller coupling area that results from decreasing the overall cell size. Alternatively, some have added a nitride layer with the thin oxide to overcome these difficulties while maintaining a high level of capacitive coupling. But this technique will not compensate for continued cell size reductions beyond some limit.
Another obstacle to downward scaling of PROM, EPROM and EEPROM arrays is the problem of providing adequate electrical isolation between adjacent cells. The conventional technique is to separate cells by isoplanar oxidation. That is, a thick field oxide is grown on the silicon substrate surface in areas around where the individual memory cells are to be formed, thus providing an electrical separation. This technique suffers from an encroachment of the field oxide into the cell area by a gradually decreasing thickness portion, known as a "bird's beak" because of its shape when viewed in cross-section. This gradually decreasing field oxide thickness region contributes little to isolation of adjacent cells, but takes up a considerable amount of space. Also, stresses associated with the thick field oxide formations along the bird's beak can result in defects, particularly when that transition region is made to be more abrupt. There has been some thought of etching away the bird's beak portion and then forming the cell in the enlarged substrate area formed by the etching, but it is difficult to etch a varying thickness oxide layer without damaging the underlying silicon substrate surface. As a result, the formation of a cell over such regions is not desirable.
Yet another limitation to the downward scaling of the size of a flash EEPROM memory array exists where the floating gate is processed to provide asperities on a surface area that is capacitively coupled to an erase gate through a tunnel dielectric layer between them. Since electrons travel from the floating gate to the erase gate during an erase operation, the asperities need to be formed on the floating gate. This requires, with currently utilized processes, that the polysilicon layer for the floating gates be formed before the polysilicon layer for the erase gates. This usual procedure can be a constraint on scaling, however. Further, this known asperity-enhanced electron tunneling has a limited endurance to the number of memory cell writing and erasing cycles that the erase dielectric can endure. This is thought to be due primarily to the trapping of electrons in the tunnel dielectric in the vicinity of the floating gate asperities.
Accordingly, it is a primary object of the present invention to provide a technique for scaling down EPROM or EEPROM cell arrays beyond that which is possible by use of current techniques having the foregoing limitations.
It is another object of the present invention to provide an EPROM or EEPROM structure which retains efficient programming, erasing, reading, and immunity to disturbing conditions, even when the memory cells are extremely small.
It is a further object of the present invention to provide an EPROM or EEPROM structure with an improved cell isolation and smaller cell size.
It is yet another object of the present invention to provide an EPROM or EEPROM cell having a planer topology and which has a high degree of insensitivity to misalignment between photo masks which are used to define critical layers.
A further object of the present invention is to provide a flash EEPROM structure having an improved endurance to repetitive programming and erasing cycles.
It is also an object of the present invention to provide very dense arrays of EPROM or EEPROM cells, thereby to increase the storage capacity of a memory array formed on an integrated circuit chip of reasonable size.